Sort and Uniq
:%!sort -u
:sort | !uniq
String Substitution Partially
发信人: Invader (政治局局长@real.complex.world), 信区: Perl
标 题: Re: 请教：字符串部分替代
发信站: 水木社区 (Fri Mar 20 13:52:47 2009), 转信
s/PATTERN/EXPR/e
标志e指示perl把EXPR作为表达式来求值，以求值结果作为替换字符串
如果待处理字符串中[]的位置固定，那么也可以直接对substr执行修改操作:
$str = "a [b c] d";
substr($str, 2, 5) =~ tr/ /-/; # $str 变为 "a [b-c] d"
下面是使用substr方法解决原问题的一种思路:
$str = "abc 123 [john jack jim jason] 8 8 8 [x y z]";
my ($a, $b) = (0, 0);
while ( ($a = index $_, "[", $b) >= 0
and ($b = index $_, "]", $a) >= 0 )
{
substr($_, $a, $b-$a+1) =~ tr/ /-/;
}
标 题: Re: 请教：字符串部分替代
发信站: 水木社区 (Fri Mar 20 00:48:18 2009), 转信
$str =~ s/\[([^][]*)\]/ ( my $data = $1 ) =~ s{\s+}{-}g ; "[$data]" /eg ;
累死我了
总体思想是找到 [ ] 之间的部分，然后用 s/\s+/-/g 替换 ，再返回
用了 /e ,
\[([^][]*)\] 即找到 [ ]之间的部分，但是内部不能嵌套 [ ] ,即单独的一对 []
用了字符类
【 在 LenovoX300 (Lenovo Thinkpad X300) 的大作中提到: 】
: 标 题: 请教：字符串部分替代
: 发信站: 水木社区 (Thu Mar 19 15:33:42 2009), 转信
:
: 比如有字符串：
: "abc 123 [john jack jim jason] 8 8 8 [x y z]"
: 如何把[]里面里面的所有空格变成-，最后变成
: "abc 123 [john-jack-jim-jason] 8 8 8 [x-y-z]"
List All Files After A Given Day
#!/usr/bin/perl
#list files editted after a given day in a directory
use File::Find;
use File::stat;
use Time::localtime;
my $base_dir = "/proj/bbic3/h2/ap/APPS_TAG_02SEP2008";
my $base_date = "20090303";
open mod_list, ">mod_list";
find(\&do, $base_dir);
sub do {
/\.v$/ or return;
$filename = $_ ;
(-f $filename) or return;
$fullname = "$File::Find::dir/$filename";
if (file_modified($_)) {
print "Found: $fullname updated on $date_string\n";
print mod_list "$fullname\n";
}
}
sub file_modified {
$file = shift;
$date_string = ctime(stat($file)->mtime);
$date_string =~ s/^\S+\s//;
$date_string =~ s/\d+:\d+:\d+\s//;
$date_string =~ s/Jan/01/;
$date_string =~ s/Feb/02/;
$date_string =~ s/Mar/03/;
$date_string =~ s/Apr/04/;
$date_string =~ s/May/05/;
$date_string =~ s/Jun/06/;
$date_string =~ s/Jul/07/;
$date_string =~ s/Aug/08/;
$date_string =~ s/Sep/09/;
$date_string =~ s/Oct/10/;
$date_string =~ s/Nov/11/;
$date_string =~ s/Dec/12/;
$date_string =~ s/(\d+)\s(\d+)\s(\d+)/$3$1$2/;
return ($date_string gt $base_date);
}
Index function in Perl
index function is used to find out if there is specified sub-string in a string.
* index STR,SUBSTR,POSITION
* index STR,SUBSTR
The index function searches for one string within another, but without the wildcard-like behavior of a full regular-expression pattern match. It returns the position of the first occurrence of SUBSTR in STR at or after POSITION. If POSITION is omitted, starts searching from the beginning of the string. POSITION before the beginning of the string or after its end is treated as if it were the beginning or the end, respectively. POSITION and the return value are based at 0 (or whatever you've set the $[ variable to--but don't do that). If the substring is not found, index returns one less than the base, ordinarily -1 .
For example,
my $a = index "abcdefg", "cd";
print "a=$a";
a=2
Clock Switch With Glitch Protection
The problem with on-the-fly clock switching
Figure 1 shows a simple implementation of a clock switch, using an AND-OR type multiplexer logic.
The multiplexer has one control signal, named SELECT, which either propagates CLK0 to the output when set to “zero” or propagates CLK1 to the output when set to “one." A glitch may be caused due to immediate switching of the output from Current Clock source to the Next Clock source, when the SELECT value changes. Current Clock is the clock source currently selected while Next Clock is the clock source corresponding to the new SELECT value.
The timing diagram in Figure 1 shows how a glitch is generated at the output, OUT CLOCK, when the SELECT control signal changes. The problem with this kind of switch is that the switch control signal can change any time with respect to the source clocks, thus creating a potential for chopping the output clock or creating a glitch at the output.
The select control signal is most likely generated by a register driven by either of the two source clocks, which means that either it has a known timing relationship to both clocks, if both clocks are multiples of each other, or it may be asynchronous to at least one clock, if source clocks are not related in any way.
Switching during either clock's high state needs to be avoided without having any idea about the frequencies or phase relationship of these clocks. Fixed delay can be used to induce the gap between the start and stop time of the two source clocks, but only if a fixed relationship exists between the two clock sources. It cannot be used where either the input frequencies are not known, or the clocks are not related.
Figure 1 -- Clock switching multiplexer
Glitch protection for related clock sources
A solution to prevent glitch at the output of a clock switch where source clocks are multiples of each other is presented in Fi gure 2. A negative edge triggered D flip-flop is inserted in the selection path for each of the clock sources. Registering the selection control at negative edge of the clock, along with enabling the selection only after other clock is de-selected first, provides excellent protection against glitches at the output.
Registering the select signal at negative edge of the clock guarantees that no changes occur at the output while either of the clocks is at high level, thus protecting against chopping the output clock. Feedback from one clock's selection to the other enables the switch to wait for de-selection of the Current Clock before starting the propagation of the Next Clock, avoiding any glitches.
The figure 2 timing diagram shows how the transition of the SELECT signal from 0 to 1 first stops propagation of CLK0 to the output at the proceeding falling edge of CLK0, then starts the propagation of CLK1 to the output at following negative edge of CLK1.
There are three timing paths in this circuit that need special consideration — the SELECT control signal to either one of the two negative edge triggered flip flops, the output of DFF0 to input of DFF1, and the output of DFF1 to the input of DFF0. If the signal on any of these three paths changes at the same time as the capturing edge of the destination flip flop's clock, there is a small chance that the output of that register may become meta-stable, meaning it may go to a state between an ideal “one” and an ideal “zero.”
A meta-stable state can be interpreted differently by the clock multiplexer and the enable feedback of the other flip flop. Therefore, it is required that capturing edges of both flip flops and the launch edge of the SELECT signal should be set apart from each other to avoid any asynchronous interfacing. This can be easily accomplished by using proper multi-cycle hold constraints or minimum delay constraints, as the timing relationship is known between the two clocks.
Figure2 -- Glitch-free clock switching for related clocks
Fault tolerance
At chip startup time, both flip flops DFF0 and DFF1 should be reset to the “zero” state so that neither one of the clocks is propagated initially. By starting both flip flops in “zero” state, fault tolerance is built into the clock switch.
Let's say that one of the clocks was not toggling due to a fault at startup time. If the flip flop associated with the faulty clock had started up in “one” state, it would prevent the selection of other clock as the Next Clock, and its own state is not changeable due to lack of a running clock. By starting both flip flops in “zero” state, even if one of the source clocks is not running, there is still the ability to propagate the other good clock to the output of the switch.
Glitch protection for unrelated clock sources
The previous method of avoiding a glitch at the output of a clock switch requires the two cl ock sources to be multiples of each other, such that user can avoid signals to be asynchronous with either one of the clock domains. There is no mechanism to handle asynchronous signals in that implementation.
This leads to the second method of implementing the clock switch with synchronizer circuits to avoid potential meta-stability caused by asynchronous signals. The source of asynchronous behavior could either the be SELECT signal or the feedback from one clock domain to the other, when the two clock sources are totally unrelated to each other.
As shown in Figure 3, protection is provided against meta-stability by adding one extra stage of positive edge triggered flip flop for each of the clock sources. The positive edge triggered flip flop in each of the selection paths, along with the existing negative edge triggered flip flop, guards against potential meta-stability, which may be caused by asynchronous SELECT signal or asynchronous feedback from one clock domain to the other.
A synchroniz er is simply two stages of flip flops, where the first stage helps stabilize data by latching it and later passing it on to the next stage to be interpreted by rest of the circuit.
Figure 3 -- Glitch-free clock switching for unrelated clocks
Conclusion
The hazard of generating a glitch on a clock line while switching between clock sources can be avoided with very little overhead by using the design techniques presented in this article. These techniques are fully scalable and can be extended to a clock switch for more than two clocks. For multiple clock sources, the select signal for each clock source will be enabled by feedback from all the other sources.
Verilog RTL
//Glitch Free Clock Multiplex
module gfcm (clkout, clk0, clk1, sel, rst0_, rst1_);
output clkout ;
input clk0 ;
input clk1 ;
input sel ;
input rst0_ ;
input rst1_ ;
reg ff0_s0 ;
reg ff0_s1 ;
reg ff1_s0 ;
reg ff1_s1 ;
assign clkout = (ff0_s1 & clk0) | (ff1_s1 & clk1) ;
always @ (posedge clk0 or negedge rst0_)
if (!rst0_)ff0_s0 <= 1'b0 ;
else ff0_s0 <= #1 ~sel & ~ff1_s1 ;
always @ (posedge clk1 or negedge rst1_)
if (!rst1_) ff1_s0 <= 1'b0 ;
else ff1_s0 <= #1 sel & ~ff0_s1 ;
always @ (negedge clk0 or negedge rst0_)
if (!rst0_) ff0_s1 <= 1'b0 ;
else ff0_s1 <= #1 ff0_s0 ;
always @ (negedge clk1 or negedge rst1_)
if (!rst1_) ff1_s1 <= 1'b0 ;
else ff1_s1 <= #1 ff1_s0 ;
endmodule
Clock Divided By 3
Basically we divide a clock frequency by 3 with following Verilog RTL.
always @ (posedge clk or negedge rst_)
if (!rst_)
clk_cnt <= 2'b0;
else
clk_cnt <= #1 {2{~clk_cnt[1]}} & (clk_cnt + 1);
assign clk_out = clk_cnt[1];
We have such waveform as below.
From above figure, we can see that clk_out has 1/3 frequency as clk with 30% duty-cycle. Then how can we get a 50% duty-cycle clock with the same frequency? Following RTL and waveform tells the answer.
always @ (posedge clk or negedge rst_)
if (!rst_)
clk_cnt <= 2'b0;
else
clk_cnt <= #1 {2{~clk_cnt[1]}} & (clk_cnt + 1);
always @ (negedge clk or negedge rst_)
if (!rst_)
clk_cnt1_neg <= 1'b0;
else
clk_cnt1_neg <= #1 clk_cnt[1];
assign clk_out = clk_cnt[1] | clk_cnt1_neg;
Primetime Variables
Remember to set following two variables in .synopsys_pt.setup for Primetime.
set timing_remove_clock_reconvergence_pessimism true
set timing_report_unconstrained_paths true
Get more information about Primetime variables & attribues here.
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