Clock Divided By 3

Basically we divide a clock frequency by 3 with following Verilog RTL.

always @ (posedge clk or negedge rst_)
if (!rst_)
clk_cnt <= 2'b0;
else
clk_cnt <= #1 {2{~clk_cnt[1]}} & (clk_cnt + 1);

assign clk_out = clk_cnt[1];

We have such waveform as below.



From above figure, we can see that clk_out has 1/3 frequency as clk with 30% duty-cycle. Then how can we get a 50% duty-cycle clock with the same frequency? Following RTL and waveform tells the answer.

always @ (posedge clk or negedge rst_)
if (!rst_)
clk_cnt <= 2'b0;
else
clk_cnt <= #1 {2{~clk_cnt[1]}} & (clk_cnt + 1);

always @ (negedge clk or negedge rst_)
if (!rst_)
clk_cnt1_neg <= 1'b0;
else
clk_cnt1_neg <= #1 clk_cnt[1];

assign clk_out = clk_cnt[1] | clk_cnt1_neg;